1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor (TFT), and more particularly, to a method using low-temperature polysilicon to fabricate a thin film transistor with symmetrical lightly doped drain (LDD) regions.
2. Description of Related Art
FIG. 1A to FIG. 1F are cross-sectional diagrams illustrating a method of fabricating a thin film transistor in the prior art.
Referring to FIG. 1A, a buffer layer 2 and a polysilicon layer 3 are sequentially formed on a substrate 1. An insulating layer 4, for example silicon oxide or silicon nitride, is deposited by CVD (chemical vapor deposition) on the buffer layer 2 in order to cover the polysilicon layer 3, as shown in FIG. 1B. A metal layer 5, for example aluminum or molybdenum, and a photoresist layer are formed on the insulating layer 4 sequentially. Then with lithography and etching, the photoresist layer is patterned into a patterned photoresist layer 6 with a first pattern. By taking the photoresist layer 6 as an etch protection layer, the metal layer 5 and the insulating layer 4 uncovered with the photoresist layer 6 are removed to become a gate electrode 5 and a gate insulating layer 4, respectively. After the photoresist layer 6 is removed, the polysilicon layer 3 is doped with n-type impurities of low dosage except for the region which is blocked and covered with the gate insulating layer 4 and the gate electrode 5.
Referring to FIG. 1D, another photoresist layer 7 is formed on the boundaries of the gate insulating layer 4 and the gate electrode 5. The polysilicon layer 3 is doped with n-type impurities of high dosage using the photoresist layer 7 as a mask. Thus a source region 8 and a drain region 9 are formed in the polysilicon layer 3 not blocked and covered with the second photoresist layer 7 and the gate insulating layer 4, and LDD (lightly doped drain) regions 14 are formed in the polysilicon layer 3 contacting the photoresist layer 7.
Further, referring to FIG. 1E, an insulating interlayer 10 is deposited over the entire surface of the structure after the photoresist layer 7 is removed. With lithography and etching, first contact holes 13 exposing the source and drain regions 8 and 9 are formed in the insulating interlayer 10. A source and a drain electrode 11 and 12, connected electrically to the source and drain regions 8 and 9, are then formed in the contact holes 13. Aluminum metal is used for source and drain electrodes 11 and 12.
Referring to FIG. 1F, a passivation layer 15 is formed on the insulating interlayer 10 to cover the source and drain electrodes 11 and 12. The passivation layer 15 is made of insulating material such as silicon oxide or silicon nitride. A second contact hole 17 exposing the drain electrode 12 is then formed in the passivation layer 15. A pixel electrode 16 is formed on the passivation layer 15 and connected electrically to the exposed drain electrode 12. In this case, the pixel electrode 16 is made up of a substance having transparent and electrically conductive properties.
As shown in FIG. 1D, the conventional process results in the formation of the unsymmetrical photoresist when the layer 7 lies over the gate electrode 5 on the polysilicon layer 3. The cause is misalignment during lithography.
In the liquid crystal display (LCD) panel processes, it is impossible to use only one exposure process to pattern a whole layer of a panel. In general, the LCD panel is divided into several regions, and several exposure processes are performed to the divided regions respectively. However, misalignment easily occurs in the exposing patterns in different regions. In FIG. 1D, d1 and d2 represent the thickness of the photoresist layer 7 at both sides of the gate electrode 5. If misalignment during lithography occurs, then the values of d1 and d2 are different, in some regions. For example, d1 may be greater than d2 in region, and maybe d1 may be less than d2 in other region. In this scenario, different sizes of LDD regions inevitably result.
The LDD structures are used to prevent the current in the region between the source and drain from leaking, and further to prevent the flickering problem. The conventional art teaches no reliable method for producing LDD structures with equal widths.
It is therefore an object of the present invention to provide a method of fabricating a thin film transistor having LDD regions of equal width, that is, symmetrical LDD regions.
To achieve the object of the present invention, the present invention provides a method of fabricating a thin film transistor, comprising the steps of providing a substrate; forming a polysilicon island on the substrate; forming a gate insulating layer on the polysilicon island; forming a metal layer on the gate insulating layer; forming a pair of trenches by removing the metal layer and the gate insulating layer until corresponding uncovered polysilicon regions are revealed; doping p-type impurities with a first dosage at the uncovered polysilicon regions in the polysilicon island; forming a gate electrode by removing parts of the metal layer and the gate insulating layer; and doping n-type impurities with a second dosage in the polysilicon island, wherein the regions doped with only n-type impurities are formed into a drain region and a source region on the both sides of the gate electrode, and the regions doped with both n-type and p-type impurities are formed into LDD regions.
Furthermore, the present invention provides a method of making thin film transistor for liquid crystal display panel, comprising the steps of: providing an insulating substrate; forming a buffer layer on the insulating substrate; forming a polysilicon island on the buffer layer; forming a gate insulating layer on the polysilicon island and the buffer layer; forming a metal layer on the gate insulating layer; forming a pair of trenches by removing the metal layer and the gate insulating layer until corresponding uncovered polysilicon regions are revealed; doping p-type impurities with a first dosage at the uncovered polysilicon regions in the polysilicon island; forming a gate electrode by removing parts of the metal layer and the gate insulating layer; doping n-type impurities with a second dosage in the polysilicon island, wherein the regions doped with only n-type impurities are formed into a drain region and a source region on the both sides of the gate electrode, and the regions doped with both n-type and p-type impurities are formed into LDD regions, wherein the gate electrode, the source, the drain and the LDD regions constitute a TFT (thin film transistor); forming an insulating interlayer on the buffer layer, wherein the insulating interlayer has first contact holes exposing a source and a drain region respectively; forming a source electrode and a drain electrode by filling up the first contact holes with metal; forming a passivation layer on the insulating interlayer, wherein the passivation layer has a second contact hole exposing the drain electrode; and forming a pixel electrode electrically connected to the drain electrode through the second contact hole.
The advantage of the present invention is that LDD regions with the same width are produced, thereby preventing the flickering problem.